Performance specifications of RoboDeus:

• Manufacturing technology – CMOS 16 nm, TSMC process.

• Maximum operating frequency, MHz – 1500 (CPU)/600-1000 (DSP)/600 (GPU).

• Total power consumption of the microprocessor – 100 W or less, minimizable.

• Embedded L3 cache - 16 MB.

• Dedicated Low Power Management hardware unit.

• Power voltage:

  • core power supply 1–1.2 V;

  • adjustable peripheral power supply 1.8/2.5/3.3 V.

• Package type: 2071 HFCBGA.

• Multicore heterogeneous MIMD-architecture based on standard and specialized processor cores:

  • coherent control cluster including 8 MIPS64 I6500 CPU cores with the operating frequency of up to 1500 MHz;

  • MIPS64 I6400 server processor CPU core for system control;

  • a high-performance cluster based on 16 ELcore-50 DSP cores with IC resources and external memory management capability, compatible with DELcore product line with the floating and fixed points.

• Peak performance of the DSP cluster:

  • 1 TFLOPs DP (FP64);

  • 4 TFLOPs SP (FP32);

  • 16 TFLOPs HP (FP 16).

• Total data and program memory of the cluster – 16 MB.

• Peak performance of one DSP core (operations per clock cycle):

  • 64 MAC in FP64 format;

  • 256 MAC in FP32 format;

  • 1024 MAC in FP16 format;

  • 8 MAC in INT64 format;

  • 64 MAC in INT32 format;

  • 256 MAC in INT16 format;

  • 1024 MAC in INT8 format.

• Support of backup reconfigurable control circuit.

• Embedded graphic accelerator (PowerVR Series8XT GT8540): 4 coherent cores with the operating frequency of at least 600 MHz based on PowerVR 8XT GT8540 graphic core.

• Peak performance of GPU:

  • 230 GFLOPs – in FP32 format;

  • 460 GFLOPs - in FP16 format.

• Supported standards: OpenGL, OpenCL, OpenVG.

• Support of pGPU mode with API OpenCL.

• Embedded multi-functional ISP preprocessor.

• Embedded video coding/ decoding core:

  • in the coding mode:

    • 2 multi-standard coders supporting H.265 (HEVC) and H.264 formats and all main profiles, coding speeds:

      • 1x 4K UHD (3840х1080) 60 fps;

      • 2x 4K UHD (3840х1080) 30 fps;

      • 8x Full HD (1920х1080) 30 fps;

    • simultaneous coding of up to 8 streams (4 streams per coder);

    • separate coding unit for JPEG and M-JPEG standards: up to 1 GPX/s, UHD resolution – 60 fps;

  • in the decoding mode:

    • 2 multi-standard coders supporting H.265 (HEVC) and H.264 formats and all main profiles;

    • simultaneous coding of up to 8 streams (4 streams per coder);

  • for coder/ decoder modes:

    • resolution of up to 8К;

    • colour depth – up to 10 bits per channel;

    • colour downsampling 4:0:0, 4:2:0, 4:2:2;

    • embedded microcontrollers for coding/ decoding control.

• 4-standard navigation core, ГЛОНАСС/GPS/BeiDou/GALILEO.

• Peripherals:

  • 4 DDR4 ports with 72-bit data buses (with ECC and CRC system support), bit rate - 819 Gbit/s;

  • 4 controllers with 4 PCI Express 4.0 lines each, bit rate - 16 GT/s per line;

  • 2 Ethernet MAC 1 Gbit controllers;

  • MAC Ethernet 10 Gbit + PHY;

  • NAND Flash controller with ECC (ONFI 2.2, 8/16 bit, 200 MT/s);

  • 2 SATA 3.0 controllers, bit rate - 6 GT/s each;

  • 2 USB 3.1 ports + PHY, 10 GT/s each;

  • 64 GPIO lines;

  • 3 SD/MMC ports (SDHC/SDXC, UHS-I, 104 Mbit/s) with eMMC 4.5 support;

  • 4 UART ports of 16550А type with IrDA support;

  • 4 I2C ports;

  • 2 dedicated SPI ports;

  • a dedicated I2S port;

  • a multifunctional LCD-display controller with the pixel clock of 594 MHz, HDMI video output support with the resolution of 3840x2160p60;

  • 2 MFBSP multifunctional ports (LPORT, SPI, I2S, GPIO) with an embedded DMA controller;

  • 2 MIPI CSI2 ports with the capability to connect 2 cameras, CMOS, HiSPI, LVDS interface support;

  • 8 universal 32-bit timers;

  • NOC-based switching system (Network-on-Chip) with embedded security and virtualization system;

  • MIPS EJTAG debugging and tracing architecture, IEEE1149.1-compliant (JTAG) debugging procedure, a debugging port with internal IC memory access, a subsystem for real-time program trace collection from CPU and DSP, trace output via an external port, a power management controller.

• Software tools:

  • С/C++ compiler for CPU unit;

  • С/С++/C11 compiler for DSP unit;

  • OpenCL compiler framework for GPU;

  • a binutils-based binary utility pack: assembler, disassembler, linker, librarian;

  • hardware support of primitives used in DNN neural networks.

• Integrated development and debugging environment:

  • software development tools, IC simulator and debugging tools include:

    • profiling tools for program execution on CPU;

    • profiling tools for program execution on GPU;

    • profiling tools for program execution on DSP;

    • project creation, project file compilation and project assembly yielding executable code and debugging with a program simulator and debugging board for SoC

    • program code entry and processing;

    • file compilation and program assembly;

    • syntax error detection and visual highlighting;

    • preparation of store image for loading to the target device;

    • program debugging;

  • IC simulator provides program imitation of processor core commands as well as working with memory, graphic processor (support of OpenGL and other API for GPU) and IC peripherals;

  • debugging tools provide debugging using the IC simulator and directly on the IC through JTAG port of the IC and USB port of the source computer, as well as:

    • loading programs into the memory model;

    • specifying breakpoints at a program address or a code line;

    • program launch;

    • program execution until the breakpoint or by steps, via the called function or skipping the called function;

    • informing about program halts and completion;

    • data reading from simulator memory by address or symbolic variable name at program halts;

    • data reading from memory and simulator (or IC) registers, data writing to memory and simulator registers of the IC;

    • boot loader program for creating a backup reconfigurable control circuit inside the IC.